TRELLIS

Project Trellis is the open-source hardware database and toolset enabling a complete, vendor-agnostic Verilog-to-bitstream flow for Lattice ECP5 Field-Programmable Gate Arrays (FPGAs).

TRELLIS (Project Trellis) is a critical open-source initiative: it documents the proprietary bit-stream format and internal architecture of Lattice ECP5 FPGAs. This documentation, published in a machine-readable database, allows the community to bypass vendor-locked tools. By integrating with the SymbiFlow toolchain (Yosys for synthesis, nextpnr for place and route), Project Trellis delivers a fully free and open-source path from HDL code to a functional bitstream on the ECP5 series, including devices with up to 85K logic cells and multi-gigabit transceivers. This effort democratizes access to powerful hardware, supporting everything from simple logic to complex RISC-V systems on affordable hardware like the ULX3S board.

https://prjtrellis.readthedocs.io/en/latest/